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1 features q 400.0 mb ps low jitter fully differential data path q 200mhz clock channel q 3.3 v power supply q 10ma lvds output drivers q cold sparing all pins q fast propagation delay of 3.5ns max q receiver input threshold < + 100 mv q radiation-hardened design; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 3 00 krad(si) and 1 mrad(si) - latchup immune (let > 1 00 mev-cm 2 /mg) q packaging options: - 48 -lead flatpack q standard microcircuit drawing 5962-01536 - qml q and v compliant part q compatible with ansi/tia/eia 644-199 5 lvds standard introduction the ut54 lvd m328 is an octal bus repeater utilizing low voltage differential signaling (lvds) technology for low power, high speed operation. data paths are fully differential from input to output for low noise generation and low pulse width distortion. lvds i/o enable high speed data transmission for point-to point or multi-drop interconnects. this device is designed for use as a high speed differential repeater. the ut54lvdm328 is a repeater designed specifically for the bridging of multiple backplanes in a system. the ut54lvdm328 utilizes low voltage differential signaling to deliver high speed while consuming minimal power with reduced emi. the ut54lvdm328 repeats signals between backplanes and accepts or drives signals onto the local bus. the individual lvds outputs can be put into tri-state by use of the enable pins. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . out1+ end in1+ + - out2+ in2+ + - in1- out1- out2- in2- standard products ut54lvdm328 octal 400 mbps bus lvds repeater data sheet august, 2002 figure 1 a . ut54 lvd m328 repeater block diagram (partial - see page 2 for complete diagram)
2 out1+ end in1+ + - out2+ in2+ + - in1- out1- out2- in2- out3+ in3+ + - out4+ in4+ + - in3- out3- out4- in4- out5+ in5+ + - out6+ in6+ + - in5- out5- out6- in6- out7+ in7+ + - out8+ in8+ + - in7- out7- out8- in8- clk in+ clk out+ + - clk in- clk out- enck figure 1b. ut54lvdm328 repeater diagram
3 pin description figure 2. ut54lvdm328 pinout ut54lvdm328 bus repeater 48 47 46 45 44 43 42 41 out3+ 1 in1+ 2 3 4 5 6 7 8 in3- 9 10 11 12 13 14 15 16 in3+ clk in+ clk in- in5- 17 18 19 20 21 22 23 24 in6- vss in8+ in8- out1+ vdd 40 39 38 37 36 35 34 33 clk out- out5- vdd clk out+ 32 31 30 29 28 27 26 25 out8- out6+ out7+ in1- in2- vdd in4+ in4- enck end in5+ in6+ vdd in7+ in7- out1- out2+ out2- vss out3- out4+ out4- vss out5+ vss out6- vdd out7- out8+ in2+ vss name # of pins description inn+ 8 non-inverting lvds input inn- 8 inverting lvds input outn+ 8 non-inverting lvds output outn- 8 inverting lvds output end 1 a logic low on the enable puts the lvds data output into tri- state and reduces the supply current enck 1 a logic low on the enable puts the lvds clock output into tri- state and reduces the supply current v ss 5 ground v dd 5 power supply clk in+ 1 non-inverting clock lvds input clk in- 1 inverting clock lvds input clk out+ 1 non-inverting clock lvds output clk out- 1 inverting clock lvds output
4 applications information the ut54lvdm328 provides the basic bus repeater function. the device operates as a 9 channel lvds buffer. repeating the signal restores the lvds amplitude, allowing it to drive another media segment. this allows for isolation of segments or long distance applications. the intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. the transmission media may be printed-circuit board traces, backplanes, or cables. (note: the ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.) input fail-safe: the ut54lvdm328 also supports open, shorted and terminated input fail-safe. receiver output will be high for all fail-safe conditions. pcb layout and power system bypass: circuit board layout and stack-up for the ut54lvdm328 should be designed to provide noise-free power to the device. good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. this increases the intrinsic capacitance of the pcb power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. external bypass capacitors should include both rf ceramic and tantalum electrolytic types. rf capacitors may use values in the range 0.01 m f to 0.1 m f. tantalum capacitors may be in the range of 2.2 m f to 10 m f. voltage rating for tantalum capacitors should be at least 5x the power supply voltage being used. it is recommended practice to use two vias at each power pin of the ut54lvdm328, as well as all rf bypass capacitor terminals. dual vias reduce the interconnect inductance and extends the effective frequency range of the bypass components. the outer layers of the pcb may be flooded with additional ground plane. these planes will improve shielding and isolation, as well as increase the intrinsic capacitance of the power supply plane system. naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias. frequent via placement also improves signal integrity in signal transmission lines by providing short paths for image currents which reduces signal distortion. the planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line from the internal power or ground plane(s) whichever is greater. doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. compatibility with lvds standard: in backplane multidrop configurations, with closely spaced loads, the effective differential impedance of the line is reduced. if the mainline has been designed for 50 w differential impedance, the loading effects may reduce this to the 35 w range depending upon spacing and capacitance load. terminating the line with a 35 w load is a better match than with 50 w and reflections are reduced.
5 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and l ife test . 3. test per mil-std-883, method 1012. 4. for cold spare mode (v dd = v ss ), v i/o may be -0.3v to the maximum recommended operating v dd +0.3v. recommended operating conditions symbol parameter limits v dd dc supply voltage -0. 3 t o 4 .0v v i/o voltage on any pin -0. 3 t o (v dd + 0.3v) t stg storage temperature -65 to +150 c p d maximum power dissipation 800mw t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 22 c/w i i dc input current 10ma symbol parameter limits v dd positive supply voltage 3.3 to 3.6 v t c case temperature range - 55 to +125 c v in dc input voltage , receiver inputs 0 to 2.4v dc input voltage, logic inputs 0 to v dd for end or enck
6 dc electrical characteristics 1 (v dd = 3.3v + 0.3v; -55 c < t c < +125 c) symbol parameter condition min max unit cmos/ttl dc specifications (en) v ih high-level input voltage 2.0 v dd v v il low-level input voltage gnd 0.8 v i ih high-level input current v in =3.6v; v dd = 3.6v -10 +10 m a i il low-level input current v in =0v; v dd = 3.6v -10 +10 m a v cl input clamp voltage i cl =-18ma -1.5 v i cs cold spare leakage current v in =3.6v, v dd =v ss -20 +20 ma lvds output dc specifications (out+, out-) v od differential output voltage r l = 35 w (see figure 9) 250 450 mv d v od change in v od between complimentary output states r l = 35 w (see figure 9) 35 mv v os offset voltage 1.055 1.550 v d v os change in v os between complimentary output states r l =35 w 35 mv i oz output tri-state current tri-state output, v dd = 3.6v v out =v dd or gnd + 10 ma i csout cold sparing leakage current v out =3.6v, v dd =v ss -20 +20 ma i os 2,3 output short circuit current v out + or v out = 0 v -25 ma lvds receiver dc specifications (in+, in-) v th 3 differential input high threshold v cm = +1.2v +100 mv v tl 3 differential input low threshold v cm = +1.2v -100 mv v cmr common mode voltage range v id =210mv 0.2 2.00 v i in input current v in = +2.4v, v dd = 3.6v -10 +10 ma v in = 0v, v dd = 3.6v -10 +10 ma i csin cold sparing leakage current v in =3.6v, v dd =v ss -20 +20 ma r l = 35 w v os =(v oh +v ol ) 2
7 dc electrical characteristics 1 (con"t) notes: 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenc ed to ground. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. only one output should be shorted at a time, do not excee d maximum junction temperature specification. 3. guaranteed by characterization. symbol parameter condition min max unit supply current i ccl total supply current r l = 35 w end, enck= v dd, v dd = 3.6v 220 ma iccz tri-state supply current end, enck = v ss, v dd = 3.6v 20 ma
8 ac switching characteristics (v dd = +3.3v + 0.3v, t a = -55 c to +125 c) notes: 1. guaranteed by design. 2. guaranteed by characterization. . symbol parameter conditions min max unit t phz 2 disable time (active to tri-state) high to z (see figure 7) r l = 35 w, c l = 10pf 4.5 ns t plz 2 disable time (active to tri-state) low to z (see figure 7) r l = 35 w, c l = 10pf 4.5 ns t pzh 2 enable time (tri-state to active) z to high (see figure 7) r l = 35 w, c l = 10pf 11.0 ns t pzl 2 enable time (tri-state to active) z to low (see figure 7) r l = 35 w, c l = 10pf 11.0 ns t lht 1 output low-to-high transition time, 20% to 80% (see figures 4 and 5) r l = 35 w, c l = 10pf 600 ps t hlt 1 output high-to-low transition time, 80% to 20% (see figures 4 and 5) r l = 35 w, c l = 10pf 600 ps t plhd propagation low to high delay (see figures 4 and 6) r l = 35 w, c l = 10pf 3.5 ns t phld propagation high to low delay (see figures 4 and 6) r l = 35 w, c l = 10pf 3.5 ns t skew differential skew t phld - t plhd (see figures 4 and 6) 900 ps t ccs output channel-to-channel skew (see figures 4 and 6) 500 ps
9 r r in+ pulse generator 50 w figure 4. lvds output load r in- 50 w c l d c l r l t hlt 20% 80% 0v 20% 80% t lht figure 5. lvds output transition time v diff t plhd t phld vdiff = 0v vdiff = 0v in out figure 6. propagation delay low-to-high and high-to-low
10 en t plz t pzl 50% 50% v ol 0vdiff 0vdiff v oh v dd v dd/2 v dd/2 50% t pzh t phz figure 7. output active to tri-state and tri-state to active 50% out out tccs vdiff = 0v vdiff = 0v out 0 out 1 figure 8. output channel-to-channel skew figure 9. driver v od and v os test circuit or equivalent circuit d d in d out- d out+ 2 0p f driver enabled generator 50 w r l = 35 w v od 2 0p f
11 packaging notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance to mil-prf-38535. 4. package dimensions and symbols are similar to mil-std-1835 requirement 101, configuration b. 5. lead position and coplanarity are not measured. 6. id mark symbol is vendor option. 7. with solder, increase maximum by 0.003. figure 10. 48-pin flatpack
12 ordering information ut54 lvd m328 bus lvds repeater: ut 54lvdm328 - * * * * * device type: ut54 lvd m328 bus lvds repeater access time: not applicable package type: (u) = 48-lead flatpack (dual-in-line) screening: (c) = military temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
13 ut54 lvd m328 bus lvds repeater: smd 5962 - * * * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) (g) = 5e5 rad(si) (h) = 1e6 rad(si) drawing number: 01536 device type 01 = bus lvds repeater class designator: (q) = qml class q (v) = qml class v case outline: (y ) = 48-lead flatpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) ** 01536 notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
14 notes

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